Design and Test Space Exploration of Transport-Triggered Architectures

Share/Save/Bookmark

Zivkovic, V.A. and Tangelder, R.J.W.T. and Kerkhoff, H.G. (2000) Design and Test Space Exploration of Transport-Triggered Architectures. In: Design, Automation and Test in Europe Conference and Exhibition 2000, 27-30 March 2000, Paris, France.

[img]
Preview
PDF
570Kb
Abstract:This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The method, that calculates the testability of the system, helps the designer to assess the obtained architectures with respect to test, area and throughput in the early phase of the design and selects the most suitable one. In order to create the templated TTA, the ¿MOVE¿ framework has been addressed. The approach is validated with respect to the ¿Crypt¿ Unix application
Item Type:Conference or Workshop Item
Copyright:©2000 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/16128
Official URL:http://dx.doi.org/10.1109/DATE.2000.840031
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 113013