A design for testability expert system for silicon compilers

Riessen van, R.P. and Kerkhoff, H.G. and Janssen, J.M.J. (1991) A design for testability expert system for silicon compilers. In: VLSI Test Symposium, 15-17 April 1991, Atlantic City, NJ.

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Abstract:	This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process
Item Type:	Conference or Workshop Item
Copyright:	©1991 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/16084
Official URL:	http://dx.doi.org/10.1109/VTEST.1991.208125
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