A new hierarchical approach to test-pattern generation

Weening, Edward C. and Kerkhoff, Hans G. (1991) A new hierarchical approach to test-pattern generation. In: Fourth Annual IEEE International ASIC Conference and Exhibit, 23-27 Sept. 1991, Rochester, NY.

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Abstract:	The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods
Item Type:	Conference or Workshop Item
Copyright:	©1991 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/16078
Official URL:	http://dx.doi.org/10.1109/ASIC.1991.242855
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