Scan cell design for enhanced delay fault testability


Brakel, Gerrit van and Xing, Yizi and Kerkhoff, Hans G. (1992) Scan cell design for enhanced delay fault testability. In: Fifth Annual IEEE International ASIC Conference and Exhibit, September 21-25, 1992, Rochester, NY (pp. pp. 372-375).

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Abstract:Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell
Item Type:Conference or Workshop Item
Copyright:© 1992 IEEE
Electrical Engineering, Mathematics and Computer Science (EEMCS)
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