Scan cell design for enhanced delay fault testability


Share/Save/Bookmark

Brakel van, Gerrit and Xing, Yizi and Kerkhoff, Hans G. (1992) Scan cell design for enhanced delay fault testability. In: Fifth Annual IEEE International ASIC Conference and Exhibit, September 21-25, 1992, Rochester, NY.

[img]
Preview
PDF
362Kb
Abstract:Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan cell
Item Type:Conference or Workshop Item
Copyright:© 1992 IEEE
Faculty:
Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:
Link to this item:http://purl.utwente.nl/publications/16074
Official URL:http://dx.doi.org/10.1109/ASIC.1992.270266
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page

Metis ID: 112958