Gate Delay Fault Test Generation for Non-Scan Circuits

Brakel van, G. and Gläser, U. and Kerkhoff, H.G. and Vierhaus, H.T. (1995) Gate Delay Fault Test Generation for Non-Scan Circuits. In: IEEE European Design and Test Conference, ED&TC 1995, 6-9 March 1995, Paris, France.

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Abstract:	This article presents a technique for the extension of delay fault test pattern generation to synchronous sequential circuits without making use of scan techniques. The technique relies on the coupling of TDgen, a robust combinational test pattern generator for delay faults, and SEMILET, a sequential test pattern generator for several static fault models. The approach uses a forward propagation-backward justification technique: The test pattern generation is started at the fault location, and after successful ¿local¿ test generation fault effect propagation is performed and finally a synchronising sequence to the required state is computed. The algorithm is complete for a robust gate delay fault model, which means that for every testable fault a test will be generated, assuming sufficient time. Experimental results for the ISCAS'89 benchmarks are presented in this paper
Item Type:	Conference or Workshop Item
Copyright:	© 1995 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Computer Architecture for Embedded Systems (CAES)
Link to this item:	http://purl.utwente.nl/publications/16044
Official URL:	http://dx.doi.org/10.1109/EDTC.1995.470379
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