'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption

Gierkink, Sander L.J. and Klumperink, Eric A.M. and Tuijl van, Ed and Nauta, Bram (1999) 'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption. In: 10th IEEE/ProRISC Workshop on Circuits, Systems and Signal Processing, 25 - 26 November 1999, Mierlo, The Netherlands.

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Abstract:	“Switched Biasing” is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8mm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.
Item Type:	Conference or Workshop Item
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/16031
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