Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'

Gierkink, Sander L.J. and Klumperink, Eric A.M. and Tuijl van, Ed and Nauta, Bram (1999) Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'. In: 25th European Solid-State Circuits Conference, ESSCIRC '99, 21-23 Sept. 1999, Duisburg, Germany.

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Abstract:	"Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.
Item Type:	Conference or Workshop Item
Copyright:	©1999 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/16029
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