Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

Sanduleanu, M.A.T. and Nauta, B. and Wallinga, H. (1997) Low-power low-voltage chopped transconductance amplifier for noise and offset reduction. In: 23rd European Solid-State Circuits Conference, ESSCIRC 1997, 16-18 Sept. 1997, Southampton, United Kingdom.

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Abstract:	This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW.
Item Type:	Conference or Workshop Item
Copyright:	© 1997 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/15974
Official URL:	hhttp://dx.doi.org/10.1109/ESSCIR.1997.186142
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