On the Design of a Real-Time Volume Rendering Engine

Smit, J. and Wessels, H.J. and Horst van der, A. and Bentum, M.J. (1995) On the Design of a Real-Time Volume Rendering Engine. Computer graphics, 19 (2). pp. 297-300. ISSN 0097-8930

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Abstract:	An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is given, capable of computing 750 × 750 × 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator circuit and a composition circuit, both capable to operate at very high speeds, have been designed for a 1.6 micron VLSI process. Both the interpolator and composition circuit are back from production. They have been tested and both complied with our specifications.
Item Type:	Article
Copyright:	© 1995 Elsevier Science
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Telecommunication Engineering (TE)
Link to this item:	http://purl.utwente.nl/publications/15457
Official URL:	http://dx.doi.org/10.1016/0097-8493(94)00155-R
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