Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

Krabbenborg, B.H. and Bosma, A. and Graaff de, H.C. and Mouthaan, A.J. (1996) Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15 (7). pp. 765-774. ISSN 0278-0070

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Abstract:	In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigated
Item Type:	Article
Copyright:	©1996 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Semiconductor Components (SC)
Link to this item:	http://purl.utwente.nl/publications/15123
Official URL:	http://dx.doi.org/10.1109/43.503944
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