Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing"

Klumperink, Eric A.M. and Gierkink, Sander L.J. and Wel van der, Arnoud P. and Nauta, Bram (2000) Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing". IEEE Journal of Solid-State Circuits, 35 (7). pp. 994-1001. ISSN 0018-9200

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Abstract:	Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 ¿m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%
Item Type:	Article
Copyright:	©2000 IEEE
Faculty:	Electrical Engineering, Mathematics and Computer Science (EEMCS)
Research Group:	Integrated Circuit Design (ICD)
Link to this item:	http://purl.utwente.nl/publications/14526
Official URL:	http://dx.doi.org/10.1109/4.848208
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